Aykut Dengi

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—This paper proposes a method to completely hide the functionality of a digital standard cell. This is accomplished by a differential threshold logic gate (TLG). A TLG with n inputs implements a subset of Boolean functions of n variables that are linear threshold functions. The output of such a gate is one if and only if an integer weighted linear(More)
In today's RFIC designs parasitics is of paramount importance and have first order impact on circuit performance. Interconnect parasitics and coupling among devices, interconnects, and passives need to be accurately taken into account during design. Otherwise, it may take months for an RFIC design to achieve layout and parasitic closure. Virtuoso RF(More)
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