Ayal Shoval

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A balanced transconductance-C biquad implemented in the digital subset of a 0.9-um CMOS process operates at frequencies up to 450 MHz and Q factors from a nominal value near 1 to approximately 100 with 30-40-dB dynamic range. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating(More)
The bandwidth limitation of existing backplanes has become an obstacle to meeting the increasing demand for high-data-rate wireline transmission. In order to compensate for this limitation, TX pre-emphasis, RX continuous-time linear equalizer (CTLE) and DFE are necessary [1,2]. This work presents a 4-lane transceiver implemented in 40nm CMOS technology that(More)
An area receiving significant attention both from academia and industry is data communications. Great effort is being placed at pushing data transmission rates over copper to near the Shannon limit which requires support electronics such as filters operating in the VHF range. Thus, tuning mechanisms are essential to accommodate fabrication and channel(More)
A programmable wide-range PLL has been designed in the digital subset of TSMC 3.3V, 0.25/spl mu/ technology that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design. The system is robust against temperature changes so that the stability of the system is(More)
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