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Most of architectural synthesis techniques target DSP algorithms onto multiprocessor architectures using basic functional units such as adders or multipliers. In this paper, a scheme for the partitioning of the data flow graph of a DSP application for a high-level synthesis aimed at a design using multi-modules is proposed. In the propose scheme, the(More)
Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance(More)
This paper presents a novel technique to obtain time schedules for cyclic DFGs representing DSP algorithms mapped onto multiprocessor systems with non-negligible inter-processor communication delays. In this paper, the question of optimizing the input/output delay in the presence of inter-processor communication overhead is addressed. The proposed technique(More)
In recent years a great deal of research has been conducted in the area of scheduling of DSP data flow graphs (DFG) onto multiprocessing systems. In this paper, a new processor allocation technique is proposed. Both heterogeneous and general-purpose functional units are used during the resource allocation process. The proposed technique provides the(More)
—This paper presents a technique for the minimization of the delay and sampling rate in the architectural synthesis of cyclic data flow graphs (DFGs) representing DSP algorithms taking into consideration the interconnect communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (sampling rate) with(More)