• Publications
  • Influence
EPIMap: Using Epimorphism to map applications on CGRAs
TLDR
We propose the use of re-computation as a solution for resource limitation problem in CGRA compilers to improve the performance of the kernels on CGRA. Expand
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REGIMap: Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)
TLDR
This paper significantly improves the state-of-the-art in CGRA compilers by first creating a precise and general formulation of the problem of loop mapping on CGRAs, considering the local registers, and from the insights gained from the problem formulation, distilling an efficient and constructive heuristic solution. Expand
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nZDC: A compiler technique for near Zero Silent Data Corruption
TLDR
We present an in-application instruction duplication based approach to protect programs from soft errors. Expand
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A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures
TLDR
We model several CGRA details in our compiler and develop a graph drawing based approach, split-push kernel mapping (SPKM), for mapping applications onto CGRAs. Expand
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A software solution for dynamic stack management on scratch pad memory
TLDR
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Expand
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An efficient compiler technique for code size reduction using reduced bit-width ISAs
TLDR
We present a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. Expand
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SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures
TLDR
We model several CGRA details in our compiler and develop a graph mapping based approach for mapping applications onto CGRAs. Expand
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Power-efficient System Design
This book addresses power optimization in modern electronic and computer systems. Several forces aligned in the past decade to drive contemporary computing in the direction of low power andExpand
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A predictable and command-level priority-based DRAM controller for mixed-criticality systems
TLDR
We propose a DRAM memory controller that meets these requirements by using bank-aware address mapping and DRAM command-level priority-based scheduling with preemption. Expand
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Mitigating soft error failures for multimedia applications by selective data protection
TLDR
We propose to partition the data space into failure critical and failure non-critical data, and provide a high-degree of soft error protection only to the failure critical data in Horizontally Partitioned Caches, while retaining the performance and energy consumption similar to those of a traditional cache system, with some degradation in QoS. Expand
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