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—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power consumption while improving performance. However, research has shown that power consumption and wiring complexity will be two of the major constraints that will hinder the growth of future NoCs(More)
As power dissipation in future Networks-on-Chips (NoCs) is projected to be a major bottleneck, researchers are actively engaged in developing alternate power-efficient technology solutions. Photonic interconnects is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is(More)
As communication distances and bit rates increase, opto-electronic interconnects are becoming de-facto standard/or designing high-bandwidth low-latency interconnection networks for high performance computing (HPC) systems. While bandwidth scaling with efficient multiplexing techniques (wavelengths, time and space) are available, static assignment of(More)
This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤(More)
The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology(More)
As Networks-on-Chips (NoCs) continue to become more susceptible to process variation, cross-talk, hard and soft errors with technology scaling to sub-nanometer, there is an urgent need for adaptive Error Correction Coding (ECC) schemes for improving the resiliency of the system. The goal of adaptive ECC schemes should be two fold; decrease power consumption(More)
—With the increasing number of cores in chip mul-tiprocessors, the design of an efficient communication fabric is essential to satisfy the bandwidth and energy requirements of multi-core systems. Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks. However, the conventional metallic(More)
—Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology(More)
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that(More)