Augusto Marques

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The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented. This supply voltage presents several design problems, such as the reduced signal swing and the non-zero switch-resistance in the switched-capacitor circuits. These problems are tackled in this design without the use of(More)
Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. /spl Delta//spl Sigma/ ADCs provide an efficient way of trading off speed for resolution. The switched op amp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold(More)
A high-resolution high-speed fourth order cascaded delta-sigma modulator, based on a 2-1-1 structure, is presented. The modulator is implemented with fully differential switched capacitor circuits in a standard 1 µm CMOS technology. The converter is powered by a single 5 V supply, uses two symmetrical reference voltages of 1 V, and is driven by a(More)
A highly integrated RF transceiver for GSM/GPRS/EDGE application is implemented in a 65nm SOC with BT and FM systems. Techniques are employed to minimize the coupling and interference effects among three wireless systems and results show the sensitivity and the output spectrum stay unchanged. The EDGE digital low-IF receiver achieves -110dBm sensitivity and(More)
Of several technology and architecture alternatives for >100 MHz >10 b DACs, CMOS current-steering DAC architectures are particularly suitable. (1) They can be designed in a standard digital CMOS technology, with evident cost and power consumption advantages in the integration with the digital circuits, and (2) They are intrinsically faster and more linear(More)
This paper presents a low-temperature coefficient VCO with a proposed frequency-drifting compensator. The compensator inside the VCO core can work both in burst-mode and continuous-mode operations. With its integration in the frequency synthesizer, no impact on spur and phase noise degradation is observed. A fractional-N synthesizer with this compensator is(More)
A DAC with 8-bit of resolution, and 12-bit of intrinsic accuracy, integrated in a standard digital 0.5 µm CMOS technology is presented. The DAC is based on a coarse-fine doubly-segmented 6+2 current steering architecture. The overall symmetry of the architecture combined with the synchronization of all blocks allows to reach a glitch energy of about(More)
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