Atulan Zaman

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Conflict-Driven Clause-Learning (CDCL) SAT solvers crucially depend on the Variable State Independent Decaying Sum (VSIDS) branching heuristic for their performance. Although VSIDS was proposed nearly fifteen years ago, and many other branching heuristics for SAT solving have since been proposed, VSIDS remains one of the most effective branching heuristics.(More)
Manifold is a generic high-level system design language designed to resemble modern functional programming languages. It is intended to be usable in a variety of design domains that can be conceptualized with components, connectors, ports, and constraints. Domain-specific backends exist for microfluidic devices and digital logic circuits. In Manifold 2.0 we(More)
The Alloy Analyzer includes a visualizer tool for presenting counter-examples to the user. This visualizer tool contains a wide array of settings and a ‘Magic Layout’ feature to automatically infer values for these settings based on a static analysis of the specification being visualized. We improve both the visualizer itself and the Magic Layout feature.(More)
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