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Power is an important issue limiting the applicability of Field Programmable Gate Arrays (FPGAs) since it is considered to be up to one order of magnitude higher than in ASICs. Recently, dynamic reconfiguration in FPGAs has emerged as a viable technique able to achieve power and cost reductions by time-multiplexing the required functionality at runtime. In(More)
This paper presents a high performance reconfiguration controller enhanced with the use of streaming lossless decompression in its data path. Two reconfiguration controllers are designed, the first is a generic controller that utilises standard concepts such as Direct Memory Access, burst mode transfer of data and interrupts to maximise throughput. This(More)
This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for(More)
This paper explores the utilization of run-time partial dynamic reconfiguration in the LEON3 open-source soft core processor, which is a highly configurable SPARC (scalable processor architecture) V8 instruction set processor. The work explores the possibilities of sharing different arithmetic functions tightly coupled to the integer pipeline and mapped to(More)
This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes(More)
This work investigates how the dynamic reconfiguration features available in modern FPGAs can be combined with a voltage-frequency scaling strategy to adapt the processing performance available in the system to the available energy budget. As defined by a hardware operating system, each processing node can configure itself as a virtual processor able to(More)
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