Atsuki Inoue

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Power reduction is a critical requirement in modern VLSI design due to increasing operating frequencies and circuit densities, and the emergence of portable applications. Decreasing the supply voltage, V DD, is the easiest way to reduce power consumption in CMOS circuits because switching power is proportional to VDD 2 for rail-to-rail logic swing. However,(More)
This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis. Our multi-processor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of(More)
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