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  • Atsuki Inoue
  • 2011
A supply voltage control technique for realizing low power LSI is utilized not only for general purpose processors, but also for custom ASIC thanks to advanced LSI design environments. Fine grain supply voltage control in time domain in power gating and DVFS scheme are seen as promising techniques to reduce power consumption. However, they require(More)
Power reduction is a critical requirement in modern VLSI design due to increasing operating frequencies and circuit densities, and the emergence of portable applications. Decreasing the supply voltage, V DD, is the easiest way to reduce power consumption in CMOS circuits because switching power is proportional to VDD 2 for rail-to-rail logic swing. However,(More)