Atanu Kundu

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In the present study, a look up table (LUT) based approach is used to extract device characteristics of an SOI based UDGMOSFET built in TCAD and imported to Cadence Virtuoso to implement analog circuit blocks. In particular, this study utilizes the custom 14nm UDGMOSFET to build a simple CMOS inverter, a single ended voltage amplifier and a Schmitt Trigger(More)
This paper consists of comparative study of U-DG-GS-NMOSFET for different channel lengths(Lch). Channel length below 100 nm leads to Short Channel Effects (SCEs). Gate Induced Drain Leakage (GIDL) and Drain Induced Barrrier Lowering are the major problem for any short channel device. Gate Stack arrangement is used to reduce GIDL and source-drain underlap(More)
In this paper the effects of channel engineering on device performance in Symmetric Underlap Gatestack DoubleGate NMOSFET has been thoroughly analyzed. A device with undoped channel has been compared with two devices having doping in source and drain side respectively. It has been observed that the graded channel with heavily doped source side offers(More)
In this paper, analog/RF performance of symmetric and asymmetric Double Gate MOSFETs (DGMOS), with an optimized underlap length, have been compared and analyzed. High k material (HfO<inf>2</inf>) with SiO<inf>2</inf> padding is used to reduce gate tunneling and scattering of electrons respectively. The on current (I<inf>ON</inf>), transconductance(More)
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