Assim Boukhayma

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—In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low noise CIS readout chain. It is shown that dramatic noise reduction is obtained by using a thin oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed(More)
—For a CIS readout chain based on 4T pixel, column amplification and CDS, we confirm that thermal noise can be reduced to be neglected compared to 1/f noise using parameters independent of the pixel design, namely column level gain, bandwidth control or correlated multiple sampling (CMS). Based on analytic noise calculation and simulation results using(More)
—This paper presents the two main circuit techniques, namely autozeroing (AZ) and chopper stabilization (CS), that are used to reduce the 1/f noise and offset in amplifiers typically used in sensor electronics interfaces. After recalling their main properties, it looks into recent trends in circuit noise reduction techniques. First, the correlated multiple(More)
—After a brief review of the principle of correlated multiple sampling (CMS) and its implementation techniques in CIS readout chains, a simple CMS passive circuit that (i) requires no additional active circuitry, (ii) has no impact on the output dynamic range and (iii) does not need multiple analog-to-digital conversions (faster) is presented. The proposed(More)
This paper explores a new way to reduce the readout noise for CMOS image sensors by using a typical 4T pixel embedding a PMOS source follower with reduced oxide thickness and gate dimensions. This approach is confirmed by a test chip designed in a 180 nm CIS CMOS process, and embedding small arrays of the proposed new pixels together with state-of-the-art(More)
This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are(More)
— A sub-0.5 e − rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18 µm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source(More)
—This paper presents a new analytical method to simply estimate the integrated thermal noise in switched-capacitor filters (SCF). It is shown how the Bode theorem, which is theoretically valid only for continuous-time passive filters, can be extended to also estimate the noise in active SCF built with operational transconductance amplifiers (OTAs).
This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source(More)