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—The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intrachip and off-chip communication on the overall power budget. The low loss properties of optical waveguides,(More)
As multicore architectures prevail in modern high-performance processor chip design, the communications bottleneck has begun to penetrate on-chip interconnects. With vastly growing numbers of cores and on-chip computation , a high-bandwidth, low-latency, and, perhaps most importantly , low-power communication infrastructure is critically required for next(More)
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electronic NoCs do not directly address the power budget problem that limits the design of high-performance chips in nanometer technologies. We make the case for a hybrid approach to NoC(More)
—We experimentally validate a complete optical packet switched interconnection network, implementing the SPINet architecture. The scalable photonic integrated network (SPINet) architecture capitalizes on wavelength division multiplexing (WDM) to provide very large transmission bandwidths, simplify network design, and reduce the network's power dissipation.(More)
Alternative contention resolution techniques are studied in the data vortex in-terconnection network, namely, the insertion of fiber-delay-line (FDL) buffers into the switching nodes. The performance of each technique is evaluated according to relevant performance metrics: acceptance rate, mean latency, and latency variance. A detailed discussion concludes(More)
We report on the implementation of a complete 12-port Data Vortex optical packet switching fabric containing 36 fully-interconnected nodes. Correct routing behavior is verified for 14-channel WDM packets, and latencies below 60 ns are achieved. 1. Introduction One of the most critical challenges for next-generation high-performance computing systems is the(More)
As high-performance processors move towards multi-core architectures, packet-switched on-chip networks are gaining wide acceptance as interconnect solutions that can directly address the bandwidth and latency requirements as well as provide partial relief to the broader challenge of power dissipation. Still, studies show that the power consumed by on-chip(More)