Ashraf Salem

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In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the(More)
In this article, a denotational definition of synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose formal model for System C delta delay. Also, we give a complete semantic definition for the languageýs two-phase scheduler. The proposed semantic can constitute a(More)
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator, where each clause is modeled as a shift register that is either right shifted, left shifted, or standstill according to whether the current assigned variable value satisfy,(More)
Multi-processor system-on-chip (MPSoC) is an integrated circuit containing multiple cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on single chip. The most crucial things in such like these systems are the performance, energy, power and area optimization. Moreover, scheduling the tasks(More)
A high performance algorithm for scheduling of tasks aims to optimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the multiprocessor systems such that the precedence constraints among the tasks are preserved. In this paper, we propose an algorithm to get the optimality of scheduling for(More)
BACKGROUND Performance of procedures on the recently dead for physician training is controversial. It has been suggested that permission be obtained. We investigated whether patients and family members would grant such permission or if even this request might anger the recently bereaved. METHODS Physicians administered identical surveys to adult emergency(More)
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five-stage pipelined SAT solver. SAT solving is broken into five stages: variable decision, variable effect fetch, clause evaluation, conflict detection, and conflict analysis. The solver(More)
We propose a new flow for hardware/software co-design that forms a base for further automation attempts of the co-design process. Our proposed flow starts with a software-only solution in which all system functionality is described as embedded software written in C targeting a selected platform. Then, the flow iterates through co-verification, profiling,(More)