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Phase-noise cancellation makes it possible to greatly widen the loop bandwidth of a ΔΣ fractional-N PLL without the massive increase in phase noise that would otherwise be caused by the ΔΣ quantization noise [1-4]. This allows the loop filter to be integrated on-chip, reduces sensitivity of the VCO to pulling and noise, better attenuates in-band VCO noise,(More)
A major problem with fractional-N PLLs is that their phase noise contains fractional spurs, i.e., spurious tones at multiples of f ref times the fractional part of f out /f ref , where f out and f ref are the PLL output and reference frequencies, respectively. In prior fractional-N PLLs fractional spurs within the loop BW tend to be large, typically well(More)
—This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the 16 modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms,(More)
A major problem in oversampling digital-to-analog converters and fractional-N frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a(More)
II. Complex Filtering An architecture for a 1.9 GHz PCS receiver is described. This architecture uses a single IF and a Complex Bandpass Sigma-Delta Modulator (BPEAM) to digitize the signal at the IF. This demonstrates the feasibility of this type of modulator in I/Q radios. Image rejection is then done in DSI? A fourth order XA modulator has been realized(More)
A novel digital frequency synthesis (DDS) architecture with a 1-bit output is proposed, simulated, and demonstrated. A new noise shaping quantization algorithm is also evaluated and used within the proposed DDS system. Large tuning ranges and rapid (open loop) response characteristics are achieved with only a static reference frequency input, without the(More)
Figure 12: a) High-level block diagram of the segmented quantizer; b) quantization block details; c) signal processing model .. Figure 16: Estimated power spectra of a) the quantization noise sequences, and b) the running sums of the quantization noise sequences of the first-order ∆Σ modulator and the segmented quantizer presented in Section IV before and(More)
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