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—As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the(More)
This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless(More)
Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and(More)