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—As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the(More)
Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and(More)