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When address reference degrees of spatial and temporal higher order address lines carry streams exhibit high locality, many of the redundant information. By caching the higher order portions of address references in a set of dynamically allocated base registers, it becomes possible to transmit small register indices between the processor and memory instead(More)
The queue-read queue-write asyn-chronous PRAM model. Parallel algorithms for shared-memory machines. The directory-based cache coherence protocol for the DASH multiprocessor.tion of a portable nested data-parallel language. 33 Proof. The lower bound for deterministic algorithms follows by the lower bound in BKK94] and Lemma 8.2 since the size of the input(More)
We analyze the information content of several address reference streams. Our results indicate that a new scheme, based on Dynamic Huffman Coding [Vitt87], can encode a typical 32 bit address in four to seven bits. Unlike previous schemes used to estimate the information content of address words [HaDa771 ~arnm77], our scheme is completely on-line and does(More)
Recent increases in VLSI processor speed and transistor density have not been matched by a proportionate increase in the number of I/O pins used to communicate information on and off chip. Since the number of I/O pins is limited by packaging technology and switching constraints, this trend is likely to continue, and I/O bandwidth will become the primary(More)
We develop a coding scheme that reduces switching transients by limiting the number of lines that simultaneously switch during transmission of address and data information over the I/O pins of a VLSI chip, or the lines of a system bus. The maximum number of lines that simultaneously switch can be reduced by a factor of two using simple and fast circuitry(More)