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In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. However, application mapping on SPMs remain a challenge. We propose a dynamic SPM management scheme for program stack data for processor power reduction. As opposed to previous efforts, our(More)
Many programmable embedded systems feature low power processorscoupled with fast compiler controlled on-chip scratchpad memories (SPMs) toreduce their energy consumption. SPMs are more efficient than caches in termsof energy consumption, performance, area and timing predictability. However,unlike caches SPMs need explicit management by software, the quality(More)
A dynamic scratch pad memory (SPM) management scheme for program stack data with the objective of processor power reduction is presented. Basic technique does not need the SPM size at compile time, does not mandate any hardware changes, does not need profile information, and seamlessly integrates support for recursive functions. Stack frames are managed(More)
BACKGROUND Femoroacetabular impingement has been postulated as the important cause of primary osteoarthritis in non dysplastic hips. We postulated that the rarity of primary osteoarthritis of hip in Indian population could be attributable to morphological differences, specifically to a lower prevalence of abnormal head-neck morphology. We conducted an(More)
The current literature on femoroacetabular impingement (FAI) is focused on acetabular orientation and femoral head asphericity, with little emphasis on the effect of version of the femoral neck. A biomechanical model was developed to determine the causative effect, if any, of femoral retroversion on hip contact stress and, if present, delineate the type of(More)
1. ABSTRACT: Today's Microprocessors consists of millions of transistors operating at extraordinarily high speeds. Verification and Test of these high performance devices continuously challenges engineers in the microprocessor design cycle. This paper gives a broad perspective of the field of microprocessor testing. Understanding of the design flow of a(More)
BACKGROUND iatrogenic devascularization of the femoral head is as an area of concern following hip resurfacing arthroplasty, with probable implications on short-term failure and long-term survival of the implant. MATERIALS AND METHODS we assessed the vascularity of 25 resurfaced femoral heads in 20 patients by comparison with preoperative and(More)
The pursuit for higher performance and higher power-efficiency in computing has led to the evolution of multi-core processor architectures. Early multi-core processors primarily used the shared memory multi-processing paradigm. However, the conventional shared memory architecture, due to its limited scalability becomes a performance bottleneck. Newer(More)
Today's embedded processors face multi-faceted challenges in the form of stringent performance, area, power and time-to-market requirements. There is a perpetual demand for embedded processors with lower power, yet higher performance, especially in personal wireless communication and multimedia domains. The 2's complement number system imposes a fundamental(More)
By 2011, the Integrated Circuit(IC) feature sizes are expected to be reduced to 22nm from present day 45nm, and the soft error rate will increase by 3 to 4 orders of magnitude (from one per year to one per hour). International Technology Roadmap for Semiconduc-tors(ITRS) indicates that techniques for mitigating soft errors are crucial for future generations(More)