Arun Bhanu

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Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible to trade correctness of circuit operations for potentially significant energy saving. For systematic design of probabilistic circuits, accurate mathematical models are(More)
A methodology has been proposed recently to predict error-rates of probabilistic circuits having a cascade structure. The objective of this poster is two fold. First, the methodology is applied, for the first time in the literature, to a probabilistic carry select adder, which has a more complex structure than the adders mentioned in previous papers.(More)
In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based(More)
This paper proposes a mathematical model for probabilistic ripple-carry adders. The model gives explicit expressions for calculating error probabilities of sum and carry bits. The expressions show how errors propagate through the carry, which accumulate and eventually influence the correctness of a ripple-carry adder's outputs. The proposed model is(More)
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