Arturo Diaz-Perez

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This report describes the design and implementation results in FPGAs of a scalable hardware architecture for computing modular multiplication in prime fields GF(p), based on the Montgomery multiplication (MM) algorithm. Starting from an existing digit-serial version of the MM algorithm, a novel digit-digit based MM algorithm is derived and two hardware(More)
Given the wide acceptance of SMS in mobile devices,it has been applied in unconventional applications beyond chating and exchanging short text messages. In this paper, we review a set of unconventional SMS-based applications. We review the basic operation modes in which they act and their needs for security services. Considering limitations on mobile(More)
This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(<i>p</i>) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form &#946; =(More)
This work presents an evaluation of different software implementations of algorithms to compute the most demanding operation in cryptographic schemes based on Elliptic Curve Cryptography (ECC), the scalar multiplication. Five different methods were studied, including traditional and more sophisticated methods for elliptic curve cryptography defined over(More)
This work describes novel hardware architectures for GF(2<sup>k</sup>) multipliers using a digit-digit approach. Contrary to the bit-serial and digit-serial approaches previously addressed in the literature, we consider the partition of the multiplier, multiplicand and modulus in several digits and execute a field multiplication in an iterative way, like in(More)
This work describes FPGA hardware architectures of GF(2<sup>m</sup>) multipliers being more compact than a bit-serial multiplier and outperforming software counterparts. The proposed multiplier is more compact than a hardware implementation of the bit-serial approach, considered the most compact one. Also, the designs proposed still outperform software(More)
This paper presents a novel FPGA-based design for the lightweight block cipher PRESENT and its implementation results. The proposed design allows to study area-performance trade-offs and thus constructing smaller or faster implementations. When optimized by area, the proposed design exhibits smaller latency and fewer FPGA resources than representative(More)