Arturo Diaz-Perez

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This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(<i>p</i>) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form &#946; =(More)
This report describes the design and implementation results in FPGAs of a scalable hardware architecture for computing modular multiplication in prime fields GF(p), based on the Montgomery multiplication (MM) algorithm. Starting from an existing digit-serial version of the MM algorithm, a novel digit-digit based MM algorithm is derived and two hardware(More)