Arthur D. Friedman

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Description: This updated printing of the leading text and reference in digital systems testing and testable design provides comprehensive, state-of-the-art coverage of the field. Included are extensive discussions of test generation, fault modeling for classic and new technologies, simulation, fault simulation, design for testability, built-in self-test,(More)
It has been shown that the number of tests required to detect all faults in a one-dimensional unilateral combinational iterative array consisting of p cells will, in general, be proportional to p. In this paper we consider properties of such systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in(More)
This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific(More)
The use of self-checking checkers in the design of highly reliable systems has many significant advantages. It allows errors to be detected upon occurrence without testing, whether the error is caused by a permanent or intermittent fault. However, there are relatively few codes for which efficient self-checking checkers have been designed. In this paper we(More)
This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented.(More)