Learn More
A growing number of applications, often with real-time requirements, are integrated on the same System on Chip (SoC), in the form of hardware and software Intellectual Property (IP). To facilitate real-time applications, Networks on Chip (NoC) guarantee bounds on latency and throughput. These bounds, however, only extend to the Network Interfaces (NI),(More)
A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical(More)
Embedded media applications have real-time constraints such as throughput and latency. In this paper we show that a tight bound on the minimum throughput can be computed with a cyclo static dataflow model that represents the application executed on the multiprocessor system-on-chip. We identify the sources that affect the tightness of the computed bound.(More)
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor system-on-chip. An external memory that is shared between processors is a bottleneck in current and future systems. Cache misses and a large cache miss penalty contribute to a low processor utilisation. In this paper, we describe a novel cache optimisation(More)
In an embedded multiprocessor system the minimum throughput and maximum latency of real-time applications are usually derived given the worst-case execution time of the software tasks. Derivation of the worst-case execution time becomes easier if it is independent of the available communication bandwidth. In this paper we show that the worst-case execution(More)
  • Jan Willem Van Den Brand, Marco Bekooij, Arno Moonen, J W Van Den Brand, M Bekooij, A Moonen
  • 2007
Multiprocessor systems-on-chip (MPSoC) with distributed shared memory and caches are flexible when it comes to inter-processor communication but require an efficient memory consistency and cache coherency solution. In this paper we present a novel consistency model, streaming consistency, for the streaming domain in which tasks communicate through circular(More)
A growing number of applications, often with real-time requirements, are integrated on the same system on chip (SoC), in the form of hardware and software intellectual property (IP). To facilitate real-time applications, networks on chip (NoC) guarantee bounds on latency and throughput. These bounds, however, only extend to the network interfaces (NI),(More)
  • 1