Armin Würtenberger

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Reducing test application time and test data volume are major challenges in SoC design. In the case of IP cores, where no structural information is available, a common strategy is to compress the test data T D provided by the core vendor into an encoded format T E. Only the smaller set T E is stored on the ATE, and during test the original test data T D are(More)
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that run-length coding, particularly alternating run-length coding, can provide high compression ratios for the test data. However, experimental data show that longer run-lengths are distributed(More)
Store-and-generate techniques encode a given test set and regenerate the original test set during test with the help of a decoder. They are particularly suitable for IP cores coming with pre-computed test sets, and they also offer a natural option for test resource partitioning, because the encoded test data can be stored either on or off chip. Previous(More)
The main factors contributing to the cost of system-on-a-chip (SOC) manufacturing test are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weights, depending on the cost model of each SOC. Several methods have been(More)
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