Arman Vassighi

Learn More
This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures. Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction(More)
What do you do to start reading thermal and power management of integrated circuits? Searching the book that you love to read first or find an interesting book that will make you want to read? Everybody has difference with their reason of reading a book. Actuary, reading habit must be from earlier. Many people may be love to read, but not a book. It's not(More)
Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation.(More)
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias.(More)
The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A(More)
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refngeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias.(More)
The leakage power is expected to inc ease with scaling of CMOS technology. The increased leakage is a strong function of the elev ted temperature and voltage stress. As a consequence, under the bum-in (BI) conditions the levated leakage power may cause increased post Burnin fallout. In this paper the impact elevated leakage and technology scaling in bum-in(More)
  • 1