Aristides Nikologiannis

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In high-speed network processors, data queueing has to allow real-time memory (de)allocation, buffering, retrieving, and forwarding of incoming data packets. Its implementation must be highly optimized to combine high speed, low power, large data storage, and high memory bandwidth. In this paper, such data queueing is used as case study to demonstrate the(More)
Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queueing is desirable. In this paper we describe the architecture(More)
One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the(More)
One of the main bottlenecks when designing a network system is very often its memory subsystem. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we describe the architecture and(More)
Ethernet technology is lo longer used only in Local Area Networks (LANs); it is continuously gaining momentum in the Metropolitan Area Net-works(MANs) and Wide Area Networks(WANs). This paper presents a multi-service access concentrator core that has been designed specifically for multi-service, purely Ethernet, access nodes. In particular the presented(More)
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