Arijit Bishnu

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Fingerprint indexing is a key technique in automatic fingerprint identification systems (AFIS). However, handling fingerprint distortion is still a problem. This paper concentrates on a more accurate fingerprint indexing algorithm that efficiently retrieves the top <i>N</i> possible matching candidates from a huge database. To this end, we design a novel(More)
This paper is concentrated on an accurate and efficient fingerprint indexing algorithm, which efficiently retrieves the top N possibly matched candidates from a huge database. In order to have ability of coping with distorted fingerprints, the proposed algorithm uses novel features, which are insensitive to distortion, formed by the Delaunay triangulation(More)
Euler number of a binary image is a fundamental topological feature that remains invariant under translation, rotation, scaling, and rubber-sheet transformation of the image. In this work, a run-based method for computing Euler number is formulated and a new hardware implementation is described. Analysis of time complexity and performance measure is(More)
Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits(More)
The coverage problem in wireless sensor network deals with the problem of covering a region or parts of it with sensors. In this paper, we address the problem of covering a set of line segments with minimum number of sensors. A line segment &#x2113; is said to be 1-covered if it intersects the sensing region of at least one among the sensors distributed in(More)
Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers placement as a graph-embedding problem and designs approximation algorithms with(More)
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithm for ASIC do not suffice. In this paper, we have proposed an algorithm for unified floorplan topology generation and sizing for recent(More)
The grid obstacle representation of a graph G = (V,E) is an injective function f : V → Z and a set of point obstacles O on the grid points of Z (where V has not been mapped) such that uv is an edge in G if and only if there exists a Manhattan path between f(u) and f(v) in Z avoiding the obstacles of O. The grid obstacle number of a graph is the smallest(More)
A new combinatorial characterization of a gray-tone image called Euler Vector is proposed. The Euler number of a binary image is a well-known topological feature, which remains invariant under translation, rotation, scaling, and rubber-sheet transformation of the image. The Euler vector comprises a 4-tuple, where each element is an integer representing the(More)