Ariel Vardi

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The paper describes the development of 60V cmos transistor for 0.18-μm Power Management shallow N Buried Layer (NBL) Platform. The device has four terminals, designed to sustain 60V. While the power implants in the platform supports drain-to-source voltage up to 60V, the gate-to-source voltage is limited to 5V by the gate oxide thickness. To extend(More)
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