Aric D. Blumer

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This paper develops a formal model of process migration that describes programs, processes, and the migration of those processes within a migration realm. A migration realm is a group of processors modeled as finite state machines. The model is motivated by a migration application between software and field programmable gate array (FPGA) hardware, and the(More)
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs). The feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle-based simulation of a Register Transfer Level (RTL) design description.(More)
With the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subset of the simulation processes is executing at any given(More)
The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization(More)
In this paper we see an approach to hardware acceleration of register transfer level simulations that utilizes Virtual Machines (VMs) and Real Machines (RMs), each executing the same instruction set. Hardware Description Language code for digital designs can lend itself well to parallel execution, and we leverage that property by executing as many processes(More)
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