Ari Y. Valero-López

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A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a(More)
The IEEE 802.11b and Bluetooth standards are two of the major driving forces of the short-range wireless communications market. Their co-existence in both home and office environments, grows constantly. As a result, a highly integrated and power efficient radio for both standards becomes an essential component for electronic products. A dual-mode(More)
In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the(More)
A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5 GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2 ,(More)
An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process(More)
Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial,(More)
This paper presents a compact, phase-locked loop (PLL) based, frequency synthesizer suitable for built-in testing and automatic tuning applications operating in the 100MHz frequency range. Key features of this design include a differential charge pump with common mode feedback (CMFB) and a voltage controlled oscillator (VCO) based on a pseudo-differential(More)
A BiCMOS frequency synthesizer compliant for both Wireless LAN (WLAN) 802.11a and 802.11b standards is presented. Proposed adaptive dual-loop PLL architecture improves reference spur rejection and settling time performance. The synthesizer is fabricated in a 0.25 μm BiCMOS process and dissipates 70 mW from a single 2.5 V supply. It occupies a silicon area(More)
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