Arash Dehzangi

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The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator(More)
The thermal treatment method was employed to prepare nickel-cobalt oxide (NiO/Co 3 O 4) nanoparticles. This method was attempted to achieve the higher homogeneity of the final product. Specimens of nickel-cobalt oxide were characterized by various experimental techniques, including X-ray diffraction (XRD), transmission electron microscopy (TEM) and Fourier(More)
We propose a new approach in device architecture to realize bias-selectable three-color shortwave-midwave-longwave infrared photodetectors based on InAs/GaSb/AlSb type-II superlattices. The effect of conduction band off-set and different doping levels between two absorption layers are employed to control the turn-on voltage for individual channels. The(More)
This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different(More)
A multi-gate n-type In 0.53 Ga 0.47 As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al 2 O 3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage(More)
A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage(More)
In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (10(15) cm(-3)) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are(More)
Polyimide/SiO(2) composite films were prepared from tetraethoxysilane (TEOS) and poly(amic acid) (PAA) based on aromatic diamine (4-aminophenyl sulfone) (4-APS) and aromatic dianhydride (3,3,4,4-benzophenonetetracarboxylic dianhydride) (BTDA) via a sol-gel process in N-methyl-2-pyrrolidinone (NMP). The prepared polyimide/SiO(2) composite films were(More)
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