Arash Ahmadi

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This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for(More)
there has been a strong push recently to examine biological scale simulations of neuromorphic algorithms to achieve stronger inference capabilities. This paper presents a set of piecewise linear spiking neuron models, which can reproduce different behaviors, similar to the biological neuron, both for a single neuron as well as a network of neurons. The(More)
— This paper presents a novel structure for the adap-tive frequency Hopf oscillator where the nonlinear function is modified to make the system realizable using analog circuit components. Mathematical model is derived and it is shown using VHDL-AMS model that despite using a new nonlinear function, the oscillator exhibits the same characteristics as the(More)
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all(More)
This study presents an analog implementation of the spiking neurons based on a piecewise-linear model. This model is a variation of the Izhikevich model, which is capable of reproducing different dynamic behaviors. The proposed circuit utilizes second generation current conveyors (CCII) building blocks. With the same topology and circuit values, this(More)
This paper addresses the problem of choosing WL optimization is conducted using the synthesized hardware different word-lengths for each functional unit in fixed-point models. In [4], a combined method of static and dynamic implementations of DSP algorithms. A symbolic-noise analysis analysis is proposed which employs an interval propagation method is(More)
This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25um technology, confirm performance of the proposed(More)
This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a(More)