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Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological sequence data has significantly out-paced Moore's law. This development also poses new computational and architectural challenges for the field of phylogenetic inference , i.e., the(More)
Two new algorithms for Golomb ruler derivation were developed and are presented together with the previously published standard algorithm. One of the new algorithms was used to prove computationally the optimality of three rulers. Two of these were previously proven but yet unpublished, and the authors' independent derivation connrmed these results. The(More)
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real(More)
1. Architecture of the TCP/IP Core This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol boosting for complex protocols such as TCP/IP. The problem was quite challenging, especially if we consider that just about all commercial implementations of TCP/IP do(More)
A new, configurable architecture has been designed and built in order to serve as a platform for experimentation with active networks. This architecture, named PLATO, provides 4 physical bi-directional connections for ATM networks, large reconfigurable resources, 256 Mbytes SDRAM for buffer space, a PCI port, and auxiliary expansion ports. Several(More)
—The most popular representative devices of re-configurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse the same hardware for different tasks at different phases of an application execution. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This(More)
As FPGA devices become larger, the trend is to have more coarse-grain modules coupled with large scale reconfigurable fabric, thus enabling new classes of applications to run efficiently compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive(More)