Learn More
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real(More)
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2–3 years. The growth of biological sequence data has significantly out-paced Moore's law. This development also poses new computational and architectural challenges for the field of phylogenetic inference, i.e.,(More)
This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol boosting for complex protocols such as TCP/IP. The problem was quite challenging, especially if we consider that just about all commercial implementations of TCP/IP do not fully implement all of the(More)
Pulse width modulation (PWM) has been widely used in power converter control. Most high power level converters operate at switching frequencies up to 500 kHz, while operating frequencies in excess of 1 MHz at high power levels can be achieved using the planar transformer technology. The contribution of this paper is the development of a high-frequency PWM(More)
Two new algorithms for Golomb ruler derivation were developed and are presented together with the previously published standard algorithm. One of the new algorithms was used to prove computationally the optimality of three rulers. Two of these were previously proven but yet unpublished, and the authors' independent derivation connrmed these results. The(More)
A new, configurable architecture has been designed and built in order to serve as a platform for experimentation with active networks. This architecture, named PLATO, provides 4 physical bi-directional connections for ATM networks, large reconfigurable resources, 256 Mbytes SDRAM for buffer space, a PCI port, and auxiliary expansion ports. Several(More)
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run efficiently, as compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive(More)