This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.
This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area… (More)