Antti Pelkonen

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To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or(More)
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products.(More)
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor’s access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the(More)
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