Antonio Trapanese

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This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of(More)
The goal of this paper is to propose a synthesis based design methodology for communication interfaces at transaction level. This methodology can guarantee the synthesizability of high level communications when IP cores each use a different type of communication structure. It also supports changes in design interface in case of IP core changes. The other(More)
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