Antonio Pullini

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In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause(More)
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a(More)
Research on <i>Networks on Chips</i> (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential(More)
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully(More)
This paper presents a lightweight cryptographic system integrated onto a multi-function implantable biosensor prototype. The resulting heterogeneous system provides a unique and fundamental capability by immediately encrypting and signing the sensor data upon its creation within the body. By providing these security services directly on the implantable(More)
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer management and allocation are fundamental tasks of each flow control scheme. Buffered flow control is the focus of this work. We consider alternative schemes (STALL/GO, T-Error, ACK/NACK)(More)
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gated and non power-gated regions within the same block. The clustering algorithm automatically selects an(More)
The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of(More)
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning "knobs" in use today in(More)