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The recent possibility of integrating multiple-OS-capable, high-core-count, heterogeneous-ISA processors in the same platform poses a question: given the tight integration between system components, can a shared memory programming model be adopted, enhancing programmability? If this can be done, an enormous amount of existing code written for shared memory(More)
Load balancing is one of the main challenges in a Virtual Machine (VM) Environment in order to ensure equal utilization of all the available resources while avoiding overloading a subset of machines. In this paper, we propose an efficient load balancing strategy based on VM live migration. Unlike previous work, our strategy records the history of mappings(More)
Current Virtual Machine (VM) live migration mechanisms only focus on providing a high availability service by offering minimal downtime to users. In this paper, we present a novel live migration technique called HSG-LM, which also aims to provide short waiting time to whoever is responsible for triggering the VM migration (e.g., the data center(More)
Given an emerging trend towards OS-capable heterogeneous-ISA multi-core processors, we address the problem of how to redesign classic symmetric multi-processing (SMP) operating systems (OS) to exploit this hardware. We propose an OS design that consists of multiple kernels, each one compiled for, and run on, a specific ISA of the heterogeneous platform.(More)
Consolidation and isolation are key technologies that promoted the undisputed popularity of virtualization in most of the computer industry. This popularity has recently led to a growing interest in real-time virtualization, making this technology enter the real-time system market. However, it has several issues due to the strict timing guarantees(More)
Migrating legacy real-time software stacks to newer hardware platforms can be achieved with virtualization which allows several software stacks to run on a single machine. Existing solutions guarantee that deadlines of virtualized real-time systems are met but can only accommodate a reduced number of systems. Therefore, this paper introduces ExVM, a new(More)
Chip manufacturers continue to increase the number of cores per chip while balancing requirements for low power consumption. This drives a need for simpler cores and hardware caches. Because of these trends, the scalability of existing shared memory system software is in question. Traditional operating systems (OS) for multiprocessors are based on shared(More)
With the emergence of both power and performance as primary design constraints, energy efficiency has become the new design criteria. A platform with heterogeneous-ISA processors can provide multiple power-performance execution points needed for a varied mix of workloads. We argue that a new system software architecture is needed to obtain maximum energy(More)
We report on our experience in implementing and evaluating nine, state-of-the-art single and multicore real-time dynamic voltage and frequency scaling (DVFS) schedulers on an embedded Linux platform. The algorithms include CC-EDF, LA-EDF, DRA, AGR, CVFS, and DR, among others, and the platform is a dual-core ARM Cortex-A9 MPCore pro-cessor/PandaBoard,(More)
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