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A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-¿m 2.5-V standard I/O FETs in a 0.13-¿m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output(More)
A single-ended digitally-modulated power amplifier (DPA) is demonstrated in a 0.13-µm 1.2-V SOI CMOS technology, to be used in a multi-standard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit amplifiers whose currents are summed at the output. The DPA is designed for multi-mode multi-band(More)
The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this(More)
In this paper a novel figure of merit for the rating of integrated transformers is presented. The proposed parameter provides a more reliable performance characterization compared to previously reported ones (i.e., insertion loss and maximum available gain), since it is inherently related to the maximization of the available output power in tuned-load RF(More)
Rapidly expanding market for multi-mode (MM) and multi-band (MB) cellular phones has recently fueled the demand for RF Power Amplifiers (PAs) that are able to operate with 2G, 2.5G and 3G standards. This trend minimizes component count, radio board size and cost while it increases power-added efficiency (PAE) needs in each operating mode as well as power(More)
A double-pole double-throw SOI CMOS switch is presented, which can be exploited to bypass a power stage in a radio transmitter with the aim of improving efficiency in applications requiring transmit power control. The switch is designed through transistors stacking. It is able to manage up to a 35 dBm input power with less than 0.35 dB insertion loss from(More)
A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (<i>V</i><sub>DD</sub> = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A(More)