Antoine Trouvé

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In this paper we propose and evaluate our platform to accelerate applications using custom instruction set extensions. We use a dynamically reconfigurable functional unit (DRFU) to execute the application specific custom instructions generated by our compiler framework. We explore two architectures with different computational granularities for the DRFU(More)
Basic block vectorization consists in extracting instruction level parallelism inside basic blocks in order to generate SIMD instructions and thus speedup data processing. It is however a double-edged technique, because the vectorized program may actually be slower than the original one. Therefore, it would be useful to predict beforehand whether or not(More)
We introduce MAD7, a tool that rapidly simulates many-core memory architectures at a functional level. MAD7 focuses on tracking access patterns and data spatial localities rather than enforcing any precise on-chip arbitration protocols. Although not cycle accurate by nature, it provides useful insights when comparing different memory architectures under(More)
In order to improve the retrieval accuracy of image retrieval systems, research focus has been shifted from designing sophisticated low-level feature extraction algorithms to combining image retrieval processing with rich semantics and knowledge-based methods. In this paper, we aim at improving text-based image retrieval for complex natural language queries(More)
This paper introduces a simple method called multimode custom instructions, which aims at reducing the power consumption of the register file of tightly coupled dynamically reconfigurable application specific instruction set processors (DR-ASIPs). To this end, it proposes to divide custom instructions into two sets depending on criteria related to their(More)