Antoine Morvan

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—Loop pipelining is a key transformation in high-level synthesis tools as it helps maximizing both computational throughput and hardware utilization. Nevertheless, it somewhat looses its efficiency when dealing with small trip-count inner loops, as the pipeline latency overhead quickly limits its efficiency. Even if it is possible to overcome this(More)
High-level synthesis (HLS) allows hardware to be directly produced from behavioral description in C/C++, thus accelerating the design process. Loop pipelining is a key transformation of HLS, as it improves the throughput of the design at the price of a small hardware overhead. However, for small loops, its use often results in a poor hardware utilization(More)
Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this(More)
—Pipelined execution is one of the most important optimizations in hardware design to improve hardware utilization rate, and hence the throughput. Loop pipelining is a transformation available in High Level Synthesis tools to execute multiple iterations of a loop in a pipeline. Nested loop pipelining is a related technique that improves hardware utilization(More)
Influence of local porosity and local permeability on the performances of a PEM fuel cell " , Turbulent Rayleigh-Bénard convection in a near-critical fluid by3D direct numerical simulation " , frequency modeling of resonated systems based on piezoelectric LiTaO3 thin layers " , Structural and optical characterization of oriented LiTaO3 thin films deposited(More)
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