Anthony S. Wojcik

Learn More
This paper describes the use of redundancy to attain a fault-tolerant design of a system. Specifically a general theory of redundancy is proposed that allows the design of fault-tolerant structures at the system-level, gate-level, or at both. The theory accounts for classic approaches to redundant design such as TMR, NMR, quadded and interwoven logics. The(More)
In present design automation systems, the standard approach that is taken to verify the correctness of proposed logic designs is that of simulation. However, due to several difficulties that arise as simulation is applied to more complex systems, designers have searched for other techniques to at least augment this traditional approach. The purpose of this(More)
The problem of nding meaningful subcircuits in a logic layout appears in many contexts in computer-aided design. Existing techniques rely upon nding exact matchings of subcircuit structure within the layout. These syntactic techniques fail to identify functionally equivalent subcircuits that are diierently implemented, optimized, or otherwise obfuscated. We(More)
A novel rule-based circuit representation is proposed to describe the connectivities of CMOS circuits at the transistor level. The unique feature of the rule-based representation is its ability to automate CMOS circuit design and verification. A precise symbolic description of the functionality of a transistor-level circuit can be derived based on a set of(More)
<i>Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it(More)