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Melsa et al. [1] presented a channel shortening technique for Discrete M ultitone transceivers that reduces Intersymbol Interference (ISI) by forcing the effective channel's impulse response to lie within a window of v+1 consecutive samples. Arslan et al. [2] claim that although this method is intuitive, no previous study has been made on its optimality.(More)
—We reformulate the minimum mean squared error (MMSE) solution for time domain equalization (TEQ) in multitone transceivers. We show that the maximum shortening signal-to-noise ratio (MSSNR) and minimum intersymbol interference (min-ISI) TEQs are particular cases of our new formulation. With good channel estimation, the MMSE-TEQ achieves near-optimal rate(More)
—This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules. Thus, rate compatibility is facilitated without the performance degradation inherent in a puncture-based system. This versatility also allows the LDPC(More)
Wavelet Packet Modulation (WPM) uses an arbitrary time-frequency plane tiling to create orthogonal subchannels of different bandwidths and symbol rates in a multichannel system. The Wavelet Packet Tree is implemented by iterating a perfect reconstruction two channel transmultiplexer. We derive operating conditions for the capacity-optimal tree for a given(More)
In this paper, we propose a novel transceiver structure for orthogonal frequency division multiple access-based uplink multiuser multiple-input multiple-output systems. The numerical results show that the proposed frequency-domain equalization schemes significantly outperform conventional linear minimum mean square error-based equalizers in terms of bit(More)
—A pilot-based channel estimation scheme is proposed for frequency selective Rayleigh fading channels which works in conjunction with the existing paradigm of turbo equalization. The iterative nature of the channel estimation technique provides substantial gain over noniterative methods and makes it a suitable choice for iterative equalization and decoding.(More)
We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32bit logarithmic arithmetic. On Virtex XCV2000E-6, it takes 22% and 27% of slices respectively and performs at 45 M Hz. The(More)