Anthony Chan Carusone

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—This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low-voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative de-coder and terminate the computations, thereby(More)
— We propose a bit-serial LDPC decoding scheme to reduce interconnect complexity in fully-parallel low-density parity-check de-coders. Bit-serial decoding also facilitates efficient implementation of wordlength-programmable LDPC decoding which is essential for gear shift decoding. To simplify the implementation of bit-serial decoding we propose a new(More)
—Multilevel clock-and-data recovery (CDR) systems are analyzed, modeled, and designed. A stochastic analysis provides probability density functions that are used to estimate the effect of intersymbol interference (ISI) and additive white noise on the characteristics of the phase detector (PD) in the CDR. A slope detector based novel multilevel bang–bang CDR(More)
—The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive(More)
—The least mean square (LMS) algorithm has practical problems in the analog domain mainly due to dc offset effects. If digital LMS adaptation is used, a digitizer (analog-to-digital converter or comparator) is required for each gradient signal as well as the filter output. Furthermore, in some cases the state signals are not available anywhere in the analog(More)
–This paper presents a 6.5 Gb/s transmitter for use in backplane links. This transmitter incorporates a finite impulse response filter with programmable tap spacing in the output driver to compensate for intersymbol interference. Using jitter-minimizing tap weights computed using a behavioral model of the transmitter, it is shown that at 6.5 Gb/s(More)
—A 40-GSamples/s track and hold amplifier (THA) is designed and fabricated in 0.18-m SiGe BiCMOS and operates from a 3.6-V supply. The total power consumption is 540 mW with a chip area of 1.1 mm 2. Time domain measurements demonstrate 40-GHz sampling and S-parameter measurements show a 3-dB bandwidth of 43 GHz in track mode. For 19-GHz input signals, a(More)
—The integration of photodetectors for optical communication into standard nanoscale CMOS process technologies can enable low cost for emerging high volume short-reach parallel optical communication. Whereas past work has highlighted the challenges that face integrated photodetectors in highly scaled CMOS technologies, this work examines the opportunities(More)
— A 3.2-Gbit/sec 2048-bit parallel LDPC decoder is implemented in a 0.18µm CMOS process. We employ two new techniques to address the interconnect problem: A broadcasting technique reduces the total amount of check-to-variable interconnect wires by more than 40%. A hierarchical placement algorithm places the variable and check nodes in the top-level(More)