Anthony Chan Carusone

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This paper describes the highest frequency PLL reported to date. It achieves the widest locking range and the lowest phase noise of −93.8 dBc/Hz at 90 GHz and 78.9 dBc/Hz at 163 GHz, both measured at a 100-kHz offset. The PLL was fabricated in a 0.13-µm SiGe BiCMOS process and covers the 81–82 GHz, 86–92 GHz, and 162–164(More)
This paper describes a single-ended integrated transversal 2-tap feed-forward equalizer implemented using a commercial 0.13-mum CMOS process. Equalization of a 38-Gb/s data stream over SMA cables with 14.3 dB of channel loss is demonstrated on-wafer. The equalizer features a microstrip transmission line as the delay element and ldquoline inductorsrdquo for(More)
This paper describes a broadband CMOS amplifier for differential receiver front-ends. A capacitive cross-coupling network provides passive g<sub>m</sub>boosting in the input cascode stage. This results in a greater than 30% increase in bandwidth. Combined with several other established bandwidth-enhancement techniques, the prototype achieves a measured 3-dB(More)
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