Anshuman Dasgupta

Learn More
The goal of the Grid Application Development Software (GrADS) Project is to provide programming tools and an execution environment to ease program development for the Grid. This paper presents recent extensions to the GrADS software framework: (1) A new approach to scheduling workflow computations, applied to a 3-D image reconstruction application; (2) A(More)
Techniques for global register allocation via graph coloring have been extensively studied and widely implemented in compiler frameworks. This paper examines a particular variant – the Callahan Koblenz allocator – and compares it to the Chaitin-Briggs graph coloring register allocator. Both algorithms were published in the 1990's, yet the academic(More)
Just-in-time compilers are invoked during application execution and therefore need to ensure fast compilation times. Consequently, runtime compiler designers are averse to implementing compile-time intensive optimization algorithms. Instead, they tend to select faster but less effective transformations. In this paper, we explore this trade-off for an(More)
For cost-sensitive or memory constrained embedded systems, code size is at least as important as performance. Consequently, compact code generation has become a major focus of attention within the compiler community. In this paper we develop a pragmatic, yet effective code size reduction technique, which exploits structural similarity of functions. It(More)
In this work, we describe new strategies for scheduling and executing Woruow applications on Grid resources using the G A D S [I31 infrastructure. Worl$low scheduling is based on heuristic scheduling srmtegies that use combined computational and memory hierarchy application component performance models. The Workflow is executed using a novel strategy to(More)
In this paper we describe the development of an efficient compiler for digital signal processors (DSP) based on the Open64 compiler infrastructure. Our development has focused on state-of-the-art DSP architectures that allow high degree of instruction level parallelism, support hardware loops, address-generation units, DSP-specific addressing features(More)
  • 1