Anshul Kumar

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This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It then throws new light on the battery recovery behavior, which can help determine optimum discharge profiles and hence result in significant improvement in battery lifetime.(More)
For a synthesis methodology to support implementation independent design specification, a capability for design space exploration is essential. In this paper we present such a methodology for a specific domain: data communication protocols. A natural way to specify various elements of protocols is in terms of a grammar annotated with actions. Our language(More)
Performance of an application can be improved through augmenting the processor with application specific functional units (AFUs). Usually a cluster of operations identified from the application forms the behavior of an AFU. Several researchers studied the impact of input and output (I/O) constraints for a legal operation cluster on the overall achievable(More)
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a(More)
This paper presents a waist-worn Pedestrian Dead Reckoning (PDR) System that requires minimal end-user calibration. The PDR system is based on an Inertial Measurement Unit (IMU) comprising of a tri-axial accelerometer, a tri-axial magnetometer and a tri-axial gyroscope. We propose a novel heading estimation scheme using a quaternion-based extended Kalman(More)
This paper presents a very efficient and versatile method to handle Dynamic Voltage Scaling for minimizing energy consumption in an embedded system processor while maintaining real time deadlines. It achieves this by creating pseudo operating frequency levels between the discrete frequency levels supported by the system, thereby addressing the root cause of(More)
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism (ILP) in applications has gone up considerably. However, monolithic register file VLIW architectures present scalability problems due to a centralized register file which is far(More)
Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment(More)
With the increase in issue width, bypass control of a processor become more complex. Also, in a processor, operands are read both from register file as well as from bypass. For a multi-port register file, read/write energy is much more than that of single port register file. Both redundant register read/write and bypass control area can be reduced with(More)