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We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach… (More)
In this paper, we introduce a fixed-point 16-bit 64 point FFT processor architecture for OFDM-based wireless applications. The processor is based on the DIT (decimation-in-time) radix-2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the… (More)
The design of an IEEE802.11 WLAN hardware MAC is presented in this paper. The function of WLAN MAC layer is partitioned between hardware and software. Timing-critical and low-level functions are implemented by the hardware MAC.
Finite fields have been used for numerous applications including error-control coding and cryptography. This paper presents a high-speed area-efficient architecture for arithmetic that can support arbitrary irreducible polynomials in GF(2<sup>m</sup>). The arithmetic unit can perform the Galois field arithmetic operations of addition, subtraction,… (More)
For VLSI design in deep submicron technology, the bus energy reduction becomes more and more important. In this paper, we modify the bus-invert coding method to maximize the power consumption reduction of data bus. Unlike the conventional scheme in which the whole bus lines are considered for bus-invert coding, our scheme partitions the bus lines into… (More)