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The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely(More)
We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si(More)
  • A J Timiyo, Yeadon­lee, +4 authors A Senior Lecturer
Users may access full items free of charge; copies of full text items generally can be reproduced, displayed or performed and given to third parties in any format or medium for personal research or(More)
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