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A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing(More)
In a separate paper, the authors show that a nonlinear active core with a fourth-order resonator can generate two stable independent frequencies simultaneously. In this paper, the effect of injecting two frequencies into such a concurrent dual-frequency oscillator is analyzed and experimentally verified. It is shown that, for weak injection, the effect of(More)
The phase noise in synchronized concurrent dual-frequency oscillators is analyzed. Two cases are considered -synchronization to external injection sources and synchronization in array of coupled identical oscillators. For small injection strengths, the phase noise behavior of synchronized concurrent dual-frequency oscillators at either of the frequencies is(More)
RATIONALE The etiology of hepatopulmonary syndrome (HPS), a common complication of cirrhosis, is unknown. Inflammation and macrophage accumulation occur in HPS; however, their importance is unclear. Common bile duct ligation (CBDL) creates an accepted model of HPS, allowing us to investigate the cause of HPS. OBJECTIVES We hypothesized that macrophages(More)
In randomized trials, longer drug-eluting stent (DES) length has been associated with adverse clinical events. We used data from the EVENT registry to examine the impact of DES length on outcomes in routine clinical practice. We identified 5,425 unselected consecutive patients from the EVENT registry who had a single vessel treated with DES for nonemergency(More)
A dual-frequency oscillator employing a fourth-order tank is shown to have the ability to generate simultaneous oscillations at two frequencies. A nonlinear analysis to determine the steady-state and transient behavior of this oscillator is presented. Further, the phase-noise expression for the dual-frequency oscillator is derived and compared with that of(More)
A digital PLL, realized in 45nm SOI CMOS, features a dual LC-tank DCO with nested inductors, achieving an octave of tuning range and area of 0.111 mm. Digital control of coupled LC-tanks creates new capabilities, enabling a 10% increase in tuning range and a 28 times reduction of DCO gain. The rms jitter, integrated from fc/1667 to fc/2, is 362 fs at 12 GHz(More)