Anisha Ramesh

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—Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models(More)
Full band atomistic modeling of homo-junction InGaAs band-to-band tunneling diodes including band gap narrowing Appl. Degenerate p-doping of InP nanowires for large area tunnel diodes Appl. Metal-oxide-oxide-metal granular tunnel diodes fabricated by anodization Appl. Resonant-tunnelling-diode oscillators operating at frequencies above 1.1THz
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