Anisha Ramesh

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—Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models(More)
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