Anis Boudabous

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This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and(More)
In this paper, we propose a low-cost sequential architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. The design targets real time application of fingerprint recognition.(More)
A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering problems. This filter is used essentially to remove impulsive and Gaussian noise in colour images. In our design we start by implementing the software solution in system on(More)
In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best(More)
In this article, multichannel image processing using an adaptive approach is the subject of our study. So we have Proposed a new Adaptive Vector Median Rational Hybrid Filter (PAVMRHF). This filter is formed by two-layered filters which combine three Adaptive Vector Median Filters in the first layer and a Rational Function in the second. Simulations'(More)
This paper proposes a novel digital signal processing implementation of vector directional distance rational hybrid filter for impulsive, Gaussian and mixed noise suppression and fine-details preservation in color images. The Implementation was done, initially, based on digital signal processing , which proves the need to a large execution time for(More)
In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW(More)
In this paper, we present a complexity study of the Gamma correction method for automatic text extraction from complex images. This study is based on the build of a simple and adequate algorithm for future hardware solution. Then, a profiling study for each function of the proposed solution was done. After validation, using C/C++ environment, a comparison(More)
Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator(More)
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