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Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to <i>k</i> variables; specifically, the logic… (More)

Due to poor correlations between pre- and post-placement timing analysis, many post-placement optimization strategies have been proposed for the FPGA CAD flow to improve circuit performance. Typically, these methods depend on logic duplication or decomposition methods combine together with incremental placement.
Circuit rewriting has proven to be a useful… (More)

Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables--specifically, the logic block is a partial… (More)

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